Anirban Sengupta

High-Level Synthesis Hardware Trojan Attacks and Countermeasures

Wed, 11 Feb 2026 15:04:49 GMT

Hardware trojans - which involve malicious modification of integrated circuits (ICs) during the design or fabrication stage - can give access to sensitive information, deny service, and so on. They can be difficult to detect but have serious consequences for the security of the IC.

Exploring hardware trojan attacks and their countermeasures using high level synthesis (HLS), this book covers different attack strategies, their detection and countermeasures, as well as future risks.

The expert author presents key information on hardware trojan attacks and their countermeasures. The book is split into four parts, starting with an introduction to hardware trojans and high-level synthesis, and then looking at various attack strategies. This is then followed by information on detection (a key issue in hardware trojan security), and countermeasures. The book finishes by looking at additional concerns and future directions of this key area in hardware security.

Readers will learn about topics such as hardware trojan classification and taxonomy, trojan attacks using malicious HLS framework, time bomb HLS-based hardware trojan attacks, trojan attacks on ML accelerator designs, other payloads of HLS trojan attack, trojan detection technique using DMR, and trojan detection and isolation technique and compromising IP designs via malicious exploitation of commercial CAD-HLS tools.

High-Level Synthesis Hardware Trojan Attacks and Countermeasures is a key resource for researchers and engineers working in hardware security and chip design.

High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection

Tue, 11 Jun 2024 14:50:41 GMT

High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection presents state-of-the art high-level synthesis methodologies for hardware security and trust, including IP protection through synthesis-based watermarking and structural obfuscation.

All modern electronic gadgets have complex system-on-chips (SoCs) that rely heavily on data intensive application specific processors, for digital signal processing (DSP), machine learning, and image processing applications. These data-intensive cores, in the form of intellectual property (IP), form an integral part of various modern equipment and consumer applications, such as smart phones, smart watches, and tablets.

High level synthesis (HLS) frameworks play a pivotal role in designing these application specific processors. However, the design of such processors can be exposed to several trust issues and hardware security threats, such as IP piracy, fraud IP ownership, and reverse engineering.

Written by an expert author, this book is a source of information for readers on HLS solutions for hardware security. It covers topics such as HLS-based watermarking using retinal biometrics, HLS-based structural obfuscation, and detective countermeasure against HLS-based hardware Trojan attacks.

This book is a useful resource for researchers, graduate students, and practising engineers working in electronics and chip design.

Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors

Fri, 03 Mar 2023 14:06:19 GMT

Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors presents state-of-the art explanations for detective control-based security and protection of digital signal processing (DSP) and machine learning coprocessors against hardware threats. Such threats include intellectual property (IP) abuse and misuse, for example, fraudulent claims of IP ownership and IP piracy. DSP coprocessors such as finite impulse response filters, image processing filters, discrete Fourier transform, and JPEG compression hardware are extensively utilized in several real-life applications. Further, machine learning coprocessors such as convolutional neural network (CNN) hardware IP cores play a vital role in several applications such as face recognition, medical imaging, autonomous driving, and biometric authentication, amongst others.

Written by an expert in the field, this book reviews recent advances in hardware security and IP protection of digital signal processing (DSP) and machine learning coprocessors using physical biometrics and DNA. It presents solutions for secured coprocessors for DSP, image processing applications and CNN, and where relevant chapters explores the advantages, disadvantages and security-cost trade-offs between different approaches and techniques to assist in the practical application of these methods.

The interdisciplinary themes and topics covered are expected to be of interest to researchers in several areas of specialisation, encompassing the overlapping fields of hardware design security, VLSI design (high level synthesis, register transfer level, gate level synthesis), IP core, optimization using evolutionary computing, system-on-chip design, and biometrics. CAD/design engineers, system architects and students will also find this book to be a useful resource.

Secured Hardware Accelerators for DSP and Image Processing Applications

Thu, 06 Aug 2020 10:42:44 GMT

Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing, which are also optimised for performance and efficiency. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators for DSP, multimedia and image processing applications are explored.

The book begins with an introduction to the principles of secured and optimized hardware accelerators for DSP and image processing applications. The following topics are then given thorough and systematic coverage: cryptography driven IP steganography for DSP hardware accelerators; double line of defence to secure JPEG codec hardware for medical imaging systems; integrating multi-key based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators; multimodal hardware accelerators for image processing filters; fingerprint biometric for securing hardware accelerators; key-triggered hash-chaining based encoded hardware steganography for Securing DSP hardware accelerators; designing N-point DFT hardware accelerator using obfuscation and steganography; and structural transformation and obfuscation frameworks for data-intensive IPs.

Intended primarily for researchers and practicing engineers, the book will also be of interest to graduate students with a particular interest in hardware device security.

Frontiers in Securing IP Cores

Wed, 07 Aug 2019 13:45:21 GMT

This book presents advanced forensic detective control and obfuscation techniques for securing hardware IP cores by exploring beyond conventional technologies. The theme is important to researchers in various areas of specialization, because it encompasses the overlapping topics of EDA-CAD, hardware design security, VLSI design, IP core protection, optimization using evolutionary computing, system-on-chip design and finally application specific processor/hardware accelerator design for consumer electronics applications.

The book begins by introducing forensic detective control and obfuscation mechanisms for hardware and IP core security. Further chapters cover hardware stenography, digital signature driven hardware authentication, fault-secured IP cores using digital signature-based watermarks, multi-level watermarking, cryptosystem-based multi-variable fingerprinting, multi-phase and hologram-based obfuscation, and security of functionally obfuscated DSP cores.